Principal PMIC Design Engineer

Industry: Electronics

Reference: BH-309

Location: Cambridge, United States

Salary: Competitive

Employment type: Permanent

Head Of Desk Jaimie Javier

Phone +44 (0) 203 9 606393

Email [email protected]

Job description

OVERVIEW

Our client is working to solve the fundamental power challenges in the mobile communications industry based on ground breaking research by two professors at the Massachusetts Institute of Technology. Today’s smartphones, wearables, and IoT devices are highly energy inefficient and typically waste most of the power consumed as heat. Our clients’ game changing Digital Envelope Tracking Technology dramatically reduces energy consumption to significantly extend the battery life of all wireless communication devices. Unlike legacy analog envelope tracking technologies, Digital Envelope Tracking Technology supports new gigabit communication standards for 5G-NR, 5G-mmWave, and WiFi.

JOB SUMMARY

The Principal PMIC Design Engineer is a senior member of the PMIC design team focused on expertise in magnetic and/or capacitive DCDC converters. This engineer is responsible for the architecture, implementation, and final performance of one major power management block in the team IC designs, and works to create, document, and file new IP. The successful candidate will have a strong track record for on-time tapeout and work well in a dynamic team environment.

KEY RESPONSIBILITIES AND ACTIVITIES INCLUDES

  • Design of analog and power management integrated circuit blocks and converters
  • Ownership of top-level power management blocks
  • Mentor and review other designers’ work
  • Interact closely with the layout engineering team
  • Contribute innovative circuits, topologies, and solutions as part of the design team

EDUCATION AND EXPERIENCE REQUIREMENTS

  • MSEE or PhD with a deep understanding of inductive and/or capacitive DCDC converters
  • Industry experience in IC design of power management solutions with production parts
  • Designing top-level magnetic and/or capacitive DCDC converter blocks
  • Power management design experience in 180nm BiCMOS or similar
  • Solid understanding of Cadence tools and use of Cliosoft revision control
  • Highly desirable: experience maintaining Cadence and Linux environment

COMPENSATION AND BENEFITS

The company offers industry-leading compensation and benefits with 401k matching, four weeks of paid vacation, flexible work arrangements where possible, medical/dental/vision/legal/life/disability insurance, wellness benefits, and more.


INTERESTED

We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Georgie Rose at PER Recruitment or send your CV to [email protected]